The embedded third generation SuperFlash® (ESF3) nonvolatile memory (NVM) gate stack is two to three times taller compared to the logic gate (LG), making it challenging to share the cell word line (WL)/erase gate (EG) polysilicon (poly) with the high-voltage/low-voltage (HV/LV) logic polysilicon. In particular, for advanced scaled poly thickness logic processes, such as the 40 nm node, there is much less margin tolerance due to the above high aspect ratio delta. A known approach uses expensive double PC masks and reactive ion etching (RIE) for achieving the advanced embedded ESF3 process. Without the double PC mask to ensure sufficient PC RIE margins for both cell and logic poly, additional polysilicon etch back is required, causing thinner EG poly above the floating gate (FG) tip region. The thinned EG poly often result in close proximity of silicide and implant damages to the tunneling oxide region, thereby causing endurance and erase performance degradation.
A need therefore exists for methodology enabling thicker EG polysilicon over the FG tip region without requiring double PC masks or additional etch back of the EG poly.